Power Optimization in TSPC D Flip-Flop Based Counters

Power optimization in a 4-bit counter is an important area of research that aims to reduce the power consumption of digital circuits while maintaining their performance and functionality. This study evaluates three different D flip-flop implementations at 45nm technology: conventional TSPC, sleeping transistors technique, and modified TSPC. A synchronous 4-bit counter was designed using flip-flops to demonstrate their performance. Comparative analysis revealed that the modified TSPC D flip-flop-based 4-bit counter outperformed both the conventional TSPC and sleeping transistors-based counters in terms of power efficiency. This indicates that the modified TSPC design is the most energy-efficient option among the three, making it a promising choice for low-power applications in 45nm technology.