Design and Implementation of High Throughput and Efficient FIR Filter Architectures Using Parallel Processing

Parallel Processing systems are multiple-input multiple-output (MIMO) system and it can be used for improving speed and reducing power consumption of a system. In parallel system, throughput of any system is increased as it process multiple outputs in parallel. In this research, a high throughput and efficient parallel system of block size 4 is developed for 11tap (10^thorder) Finite Impulse Response (FIR) filter. For designing this parallel system VHDL (VHSIC Hardware Description Language) is used and Artxi7 Basys3 FPGA board is used for implementation. This MIMO system operates at 1200KHz frequency and inputs for this MIMO system are generated by a serial to parallel converter circuits at frequency of 4800KHz. Vivado 2015.2 tool is used for doing synthesis, simulation and MATLAB is used for finding 11tap (10^thorder) FIR filter coefficients. Designed and implemented parallel system is compared for area and speed with existing serial and parallel FIR filter architectures.