Design and Analysis A High-Performance Parallel Decimal Multiplier

This paper presents a novel approach to addressing the demand for efficient decimal arithmetic units in critical applications such as tax calculation, accounting,banking, and currency conversion, with a specific focus on the multiplication operation. The proposed design methodology emphasizes power consumption analysis without compromising performance, decomposing a digit multiplier using techniques inspired by Karatsuba algorithms. The multiplicand and multiplier are partition into various sizes, including multi16-8, multi16-4, multi16-2, and multi16-8-4, and the traditional Ripple Carry Adder (RCA) is replaced with a more efficient Carry Increment Adder (CIA). The study evaluates the designed multipliers using Verilog HDL and the Xilinx ISE tool, analyzing delay, area, and power consumption. The results, based on 16-digit operands, highlight the effectiveness of approach in achieving a balance between computational performance and power efficiency in radix-10 arithmetic units.