100 Gbps Low-Latency Protocol Processing and FPGA Implementation

With the ongoing evolution of integrated space-air-ground networks, space laser communications face increasingly stringent demands for low latency and high throughput in high-speed data transmission. To meet these requirements, this paper presents a low-latency protocol stack processing architecture based on Field Programmable Gate Array (FPGA) and provides an in-depth investigation into its implementation at the hardware level. By employing a nonindependent four-channel data interface, the proposed architecture significantly enhances the alignment efficiency during the data framing and deframing processes, thereby mitigating the overhead associated with large-volume data handling. In addition, an adaptive inter-frame interval control mechanism is introduced to effectively reduce the data processing latency. Experimental validation on a Xilinx Virtex UltraScale VCU108 development board, equipped with a 100G CFP2-DCO optical module, demonstrates that the system achieves a throughput of up to 98.1 Gbps, with an end-to-end latency of approximately 300 ns. Compared to other FPGA-based solutions, which achieve a best-reported protocol processing latency of approximately $1.3~\mu $ s in existing research, our method achieves at least a 4x improvement in overall data processing speed.