Fine-Grained Modeling and Evaluation of 3-D Power Distribution Networks in Logic-on-Memory Stacking Architecture

With the escalating computing power demands in artificial intelligence-generated content and other applications, the three-dimensional (3-D) stacking technology has effectively broken through the bottleneck of Moore's law and become the primary choice for high-performance chip packaging technology. Especially in the logic-on-memory (LoM) scenario with strong industrial feasibility, the 3-D stacking process fully leverages its advantages of extremely high interconnection density and low communication delay, making it well-suited for addressing the bandwidth expansion challenges under the “memory wall” bottleneck. Nevertheless, the heightened integration level and reduced power consumption requirements of the LoM architecture have introduced significant challenges to the power supply of stacking chips. Current EDA tools lack the capability to rapidly and effectively explore the optimal design of LoM power distribution networks (PDNs), and existing SPICE-type 3-D PDN analysis models often encounter challenges with oversimplified modeling approach and idealized power analysis, rendering them unsuitable for LoM structures, such as near-memory computing and high-bandwidth processors in computing/memory stacking scenarios. In this work, we propose for the first time a fine-grained 3-D PDN analysis modeling approach designed for LoM stacking architecture. Our modeling method comprehensively accounts for the power supply characteristics within the stacking architectures, and implements fine-grained segmentation and modeling of the full-chip PDN based on the estimated area, power consumption, and backend-of-line dimensions, allowing for rapid and accurate evaluation of power integrity (PI) across different PDN design schemes before the physical design stage. Furthermore, we explore the optimal 3-D LoM PDN design across various physical design spaces, including multilayer PDN connection schemes, metal layer configuration, and through-silicon via placement density. The final analysis result is applied to guide the practical physical design of the LoM PDN, highlighting the significance of our modeling approach in 3-D chip PI analysis and 3-D PDN design optimization.