MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator

Transformer models have revolutionized natural language processing (NLP) and enabled many new applications, but are challenging to deploy on resource-constrained edge devices due to their high computation and memory demands. We present MINOTAUR, an edge system-on-chip (SoC) for inference and fine-tuning of Transformer models with all memory on the chip. MINOTAUR utilizes a configurable 8-bit posit-based accelerator to achieve highly accurate and efficient inference and fine-tuning. To minimize memory power, MINOTAUR employs fine-grained spatiotemporal power gating of on-chip resistive-RAM (RRAM). MINOTAUR enables on-chip fine-tuning through full-network low-rank adaptation (LoRA). MINOTAUR fabricates in a 40-nm CMOS process, achieves ResNet-18 inference in 8.1 mJ and MobileBERTTINY inference in 8.2 mJ, and performs on-chip fine-tuning with an accuracy that is within 1.7% of offline training.