Edge trigger and its applications

Edge Trigger is known to possess positive sensing capability by using NAND gate based Flip-Flop. On the other hand, J-K Master-Slave Flip-Flop using the same NAND gate based one negative-slope senses signals as the clock turning down to zero from high. J-K Master-Slave FF does have a lot of applications, including timer or counter design simply at J=1=K. Using the same design idea, an Edge Trigger counter is then generated. The new generated Edge Trigger counter/timer simplifies the use of number of transistors. It is then for sure an increase of transmitting speed of transferring data. Based upon TSMC 1.25µm process, Tanner software is used to verify if the design may be feasible. In addition, newly generated layout is proposed for the design and proven to be available in the Edge Trigger applications.