Random Logic Locking with Enhanced Resilience against SAT Attacks

Logic locking has recently been identified as a predominant methodology to protect integrated circuits from unauthorized access and theft. It involves the augmentation of additional key gates into the IC design, which makes it difficult for attackers to reverse engineering/tamper with the chip. But, Boolean Satisfiability (SAT)-based attack has become an effective technique to break such arrangements. As a result, various configurations have been proposed to counteract SAT attacks, focusing on strategically positioning key gates in random locations within the circuit. However, most of these protective arrangements are easily identifiable by the adversary. In this work, we proposed the location of key gates (XOR and XNOR-based) to tackle this issue. The key gates are positioned randomly in a specific part of the circuit, particularly targeting gates with higher observability values to enhance security. Also, output corruptibility is used as a metric to check the performance. Results validate that implementation of such placements can enhance resistance to SAT attacks, even when employing a random locking scheme.