Memory Management and Arbitration for Multi-Channel Duplex Communication on FPGA

Memory is an essential resource while implementing computationally intensive applications on the Field Programmable Gate Array (FPGA). When IP cores with high performance are utilized to implement external interfaces with large data rates and reliable communication link, memory is a critical resource for addressing data transfer and bandwidth requirements. Memory controller in general supports DDR2/DDR3/DDR4 SDRAM. When memory is shared between various modules of design, the memory controller has to be utilized effectively to cater for the bandwidth requirements for all modules. This paper discusses the conflict cases, management and arbitration of memory implemented with FPGA in a scenario where a core is implemented to bridge between two high speed interfaces. In which one of this interface is communicating with external environment in multiple channel configuration. It covers the information regarding hardware involved, IP cores implemented in FPGA for the communication channels data buffering, PCIe bus arbitration and effective throughput in the transfer.