A Comprehensive Analysis on Comparator, Encoder Circuit to Develop Flash Type ADC Based on Different Implementation Routes

The present paper describes the design and performance evaluation of two different flash-type analog-to-digital converter (ADC) circuits, targeting applications towards high speed and low power consumption. The first considered flash-type ADC circuit comprised of a sample and hold circuit (that is common for both the ADCs), clamped push-pull output comparator, and 8:3-bit priority encoder made up via employing basic logic gates (Case 1). The second flash-type ADC circuit comprised of an open-loop two-stage comparator, and an 8:3-bit priority encoder circuit made up using basic logic gates (Case 2). Throughout the analysis, evaluations of power consumption, propagation delay, and noise properties were investigated. The circuits were simulated in Cadence Virtuoso platform (v 6.1.5) with 90nm CMOS technology. The power consumption was found to be 31.47mW for Case 1, while in Case 2, it was 31.53mW. In addition, propagation delay and noise analysis were also carried out for a comparative study between the two cases.