Universal Gate Design Using Non-Aligned Gate Transistors: A Performance Evaluation in TCAD

This paper explores the design and performance analysis of a 270 nm compact single-device NAND and NOR structures. With the non-alignment double gate technology, the proposed design shows a reduction in the number of transistors to realize the digital gates. The performance of the proposed structures was analysed by considering the gate oxide dielectric ($k$)-metal $(\phi)$ material combinations $(k\phi)$ as the measuring index. At 1 GHz input frequency, the input pattern sensitivity of the NAND and NOR structures were analysed. Further, by using the graphical method the optimal supply voltage of the NAND and NOR gates was determined. Among various $k\phi$ combinations, the result shows a low value optimal supply voltage for the NAND and NOR gate is obtained with $\text{SiO}_{2}-\mathrm{M}2$ combination. The proposed structure shows an improvement of 69.45% in its delay performance when compared to the past works. This shows the suitability of the proposed structures at lower supply voltages.