The FOStrip® Technique - A Low-Cost Solution for the Strip Level Fan-Out on Substrate Package

This paper presents a novel method for the low-cost fanout package named FOStrip® and successfully builds up the test vehicle with a package size of 50mm x 50mm. The FOStrip is a new fan-out packaging technology developed by Kore Semiconductor Co., Ltd., which obtained a technical patent and trademark in 2018. It is a chip-last strip-level fanout package technique and is not only compatible with both wafer-level and panel-level processes in the front-end assembly process but also retains the benefit of the strip-level process in the back-end assembly process. The various strip sizes could be diced after the front-end assembly process of FOStrip to meet the requirement of each assembly house and use existing tools to execute flip chip bonding, wire bonding, underfill dispensing, molding process… etc. There is no need to invest in additional FOWLP or FOPLP equipment, effectively integrating existing resources and obtaining higher yields, significantly increasing the feasibility of mass production. In the rough estimate, the fan-out package with the substrate by using the FOStrip technique could reduce the cost by equal to or less than 30% compared with the general substrate-type packages. In addition, this study focuses on examining the warpage behavior of a 50 mm x 50 mm fan-out package after heat spreader attachment, considering various die thicknesses and lid thicknesses. To achieve this, a 3D finite element model is constructed to simulate the thermally-induced warpage, the simulation results clearly illustrate that increasing the die thickness leads to a significant reduction in warpage.