A Chip on Board Packaging Solution for 4×100Gbps PAM4 Optical Engine

In this paper, we propose a chip-on-board (COB) packaging solution for 4xl00Gbps PAM4 Optical Engine (OE). This cost-effective solution utilizes bonding wires to interconnect the Electrical Integrated Circuit (EIC), Photonic Integrated Circuit (PIC), and the printed circuit board (PCB). Specialized transition structures are designed to convert the GSGSG RF configuration into SS and GSSG. A full-wave simulation using HFSS was performed to assess the interconnects' frequency domain performance, achieving a 10dB return loss bandwidth of 30GHz and a 3dB insertion loss bandwidth of 80GHz. Additionally, time-domain eye-diagram simulations were conducted using ADS, showing a clear signal for 112Gbps but noticeable degradation at 224Gbps. The bandwidth of this solution is constrained by the RF configuration transitions and the high parasitic inductance of the bonding wires. Furthermore, a Fiber Array Unit (F AU) is attached to the edge of the PIC, with a coupling loss of 1.5 dB achieved after curing the optical adhesive.