Enhancing Design Stability and Flexibility in Partial Isolation Type LDMOS

This study comprehensively analyzes the performance variation mechanisms in partial isolation type laterally double-diffused metal-oxide-semiconductor (Pi-LDMOS) field-effect transistors. The concept of the ’silicon gap’ in this study refers to the space between the drift region and the partial insulator (Pi). For the Pi-LDMOS structure requiring fabrication verification, with p-substrate and n-drift doping concentrations of $3\times 10^{16}$ cm−3 and $5\times 10^{16}$ cm−3, respectively, high-precision software SENTAURUS TCAD simulations are conducted to analyze breakdown voltage (BV), specific on-resistance (R $_{\mathrm {on,sp}}$ ), and figure of merit (FOM) for parameter ranges of 0- $10~\mu $ m for Pi length (L $_{\mathrm {pi}}$ ), 0- $20~\mu $ m for Pi thickness (t $_{\mathrm {pi}}$ ), and 0- $1~\mu $ m for silicon gap thickness (g $_{\mathrm {pi}}$ ). The maximum BV (BV $_{\max }$ ) and maximum FOM (FOM $_{\max }$ ) in this device can be achieved by optimizing the balance between the vertex point electric field (E $_{\mathrm {T}}$ ) and the vertical point electric field (E $_{\mathrm {C}}$ ), which are modulated by Lpi and tpi variations. Acceptable range area (A $_{\mathrm {acceptable}}$ ) is defined as the rectangular area bounded by the permissible ranges of Lpi and tpi that achieve target values for both BV and FOM. Compared to g $_{\mathrm {pi}}=0.0~\mu $ m, when g $_{\mathrm {pi}}=1.0~\mu $ m, Aacceptable increases by 37.3 and 39.2 times for BV $\ge 120$ V and BV $\ge 100$ V respectively, and by 4 and 18.7 times for FOM $\ge 4.5$ MW/cm2 and FOM $\ge 4.0$ MW/cm2 respectively. Moreover, variation rate of Ron,sp ( $\Delta $ R $_{\mathrm {on,sp}}$ ) decreases from 7% to 0%. These results demonstrate that considering the silicon gap in Pi-LDMOS design can enhance design stability and flexibility through expanded design margins and consistent performance distributions in achieving the target performance.