Reduced-Delay Sigma-Delta Filter for Accurate Current Measurement in PWM VSCs

The popularity of sigma-delta measurement (SDM) in power electronics is increasing due to its high accuracy but is hampered by the significant measurement delay it introduces. This delay is further increased if the SDM's digital filter is designed to attenuate not only the quantization noise but also the pulsewidth modulation (PWM)-related harmonics. The main objective of this article is to improve the SDM methodology by adding and verifying a new digital filter, named the TSS filter, which reduces measurement delay while remaining robust against the presence of PWM ripple. Given the limited amount of published information on SDM accuracy in PWM voltage-source converters (VSCs), the secondary objective of this article is to experimentally compare it against regular sampled measurement (RSM) on a dedicated platform. To show that the resulting inaccuracies are inherent to RSM rather than stemming from poor converter design, an analysis of measurement error sources in PWM VSCs is conducted.