Experimental Estimation of Parasitic Capacitance of Thermal Interface Material Using Double Pulse Test Circuit under Realistic Operating Conditions

Thermal interface materials (TIM) are crucial for effective thermal management in power electronic converters. Thermal pads are commonly used for flat surfaces, such as those found in TO-247 packages of IGBTs and MOSFETs. However, their placement between the device base plate and the heat sink introduces parasitic capacitance, providing a dominant path for the common mode (CM) current which impacts the conducted EMI performance of the converter. The accurate prediction of CM current relies on the precise value of the parasitic capacitance. The theoretical estimates of the capacitance are inaccurate in variable temperature and frequency conditions. This paper presents an experimental method to estimate the parasitic capacitance of the TIM under near-operating conditions, which also can be adapted for actual operating conditions. It uses a double pulse test (DPT) circuit with additional arrangements. The parasitic of the components are extracted using Ansys Q3D extractor tool and impedance analyzer (Bode 100). The experimentally validated CM circuit is simplified to an equivalent series RLC branch undergoing natural response. Using CM frequency observed in the hardware waveform of the CM current, the parasitic capacitance of the TIM is estimated. Experimental validation is conducted to verify the sources and paths of the CM current, the capacitive behavior of TIM and the capacitance estimated using the equivalent RLC network.