18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Correlated Level Shifting

With the development of high-resolution ADCs (>13b) leveraging the SAR topology, the pursuit of power efficiency in ADC design continues to make remarkable strides [1]–[5]. However, as the capacitance of the capacitive DAC (CDAC) increases to satisfy the kT/C noise specification, excessive driving pressure is posed on the front-end input buffer. Furthermore, a separate higher supply voltage is typically demanded for the driver to accommodate the input swing while maintaining the linearity requirement. The increasing load and wide supply voltage often make the power consumption of the ADC core overwhelmed by the power consumption of the driving buffer, presenting a bottleneck in achieving an overall energy-efficient system. Loop-embedded buffer architectures have been explored in prior arts to reduce the linearity requirement of the buffer while easing the driving pressure of the system [2], [6]–[8]. Rail-to-rail signal swing is achieved in [7] with a dedicated capacitive level shifting bias scheme. Besides, a rail-to-rail high-linearity input buffer using a predictive level shifting technique is proposed in [3], but careful tuning of the predictor is necessary for the targeted performance.