7.10 An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS

Multi-phase clock generation is among the most critical building blocks in high-speed wireline transceivers. The integrated jitter and phase error of the clocks often dictate the maximum available SNDR at higher frequencies. While the classic method of dividing the differential clocks from a phase locked loop provides excellent phase accuracy with low jitter [1]–[8], it requires the phase locked loop to generate high frequency clocks at multiples of the output frequency $(\mathrm{f}_{\text{out}}\times \mathrm{N})$. In CMOS processes with $\mathrm{f}_{\mathrm{T}}$ of around 200-300GHz, the combination of phase locked loop and divider becomes increasingly costly, if not infeasible, in 224Gb/s PAM-4 applications and beyond [9]–[11]. Quadrature VCOs [12]–[14] and poly-phase filters [15]–[17] partly mitigate the issue, but they are sensitive to device mismatches and more importantly, only provide 4 clock phases. The delay locked loop (DLL) consisting of chains of inverters conceptually expands the input clock to any desired number of phases, at the cost of jitter accumulation and higher phase errors due to mismatch. Cascading a ring oscillator injection locked by the DLL suppresses phase error as the ring oscillator is an autonomous circuit with intrinsically strong feedback [18]–[20]. Whereas the cascading configuration offers low jitter and low phase error at the same time, the maximum operation frequency is still limited by the minimum loop delay in the ring oscillator, the frequency of which is determined by $1/(2\mathrm{m}\times \mathrm{t}_{\mathrm{d}})$ with $t_{d}$ being the delay of an inverter and m being the number of inverters.