13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost

Growing interest in healthcare has led to the development of many wearable battery-powered artificial-intelligence internet-of-things (AI-IoT) devices for continuous monitoring a wide variety of vital signs [1], [2] (Fig. 13.6.1). While analog-based compute-in-memory (CiM) ASICs are effective in reducing power consumption, it is not realistic to prepare a wide variety of ASICs each of which incurs substantial mask costs. To address this issue, a single-mask customizable fabrication scheme for low-power DNN processors utilizing via-programmable neuron array (VPNA) is proposed. While diverse DNN layers are realized by arranging the placement of vias on a uniquely designed base chip, there are two major challenges: the large area overhead of the programmable routing wires and the large number of nodes and parameters required to implement DNN layers. The bit- and neuron-serial circuit (BNSC) technique reduces the implementation area by 1/1024 for programmable wires. A sparse binary weighted DNN technology (FS-NNN) reduces DNN size and required VPNA tiles to less than 20. For the EEG task, energy efficiency is improved by 8.4x, and the number of masks required is reduced to 1/40, compared with the previous ASIC implementation.