29.2 A $\boldsymbol{0.021}\boldsymbol{\mu}\mathbf{m^{2}}$ High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery

The accelerating pursuit of high-performance and energy-efficient computing drives recent breakthroughs in both semiconductor devices and power-delivery schemes in advanced process technologies. This paper presents industry's first volume silicon validated high-current (HCC) and high-density (HDC) 6T SRAM implemented in a RibbonFET technology incorporating backside power delivery using PowerVia technology in the peripheral circuits. The RibbonFET technology offers better performance per watt and improved density; it also allows for the flexible adjustment of the effective transistor width to achieve optimal SRAM transistor sizing for power, performance and $\mathrm{V}_{\text{MIN}}$. The PowerVia technology [1]–[3] features low resistance metal layers for power delivery on the backside of the wafer that reduces power droop and frees up additional signal routing resources on the frontside interconnects to enable more efficient peripheral circuit design. Compared to similar designs [3], [4] using FinFETs, the proposed RibbonFET SRAM design achieves 0.77x and 0.88x bitcell area scaling for HCC and HDC. RibbonFET HCC measurements demonstrate an improved $\mathrm{V}_{\text{MIN}}$ without assist circuitry at the 90^th percentile, compared to prior FinFET-based designs that required both read and write assist circuitry. With a negative bitline (NBL) write assist the $34.3\text{Mb}/\text{mm}^{2}$ HDC array demonstrates a 68mV $\mathrm{V}_{\text{MIN}}$ improvement, compared to prior designs. Up to $38.1\ \text{Mb}/\text{mm}^{2}$ is achieved using an HDC SRAM with larger bit array configuration and additional peripheral circuit compaction.