37.3 Monolithic in-Memory Computing Microprocessor for End-to-End DNN Inferencing in MRAM-Embedded 28nm CMOS Technology with 1.1Mb Weight Storage

Always-on AI sensor applications–based on deep neural networks (DNNs)–with sparse inference require low power consumption during both computing and idle phases. In-memory computing (IMC) with non-volatile memory crossbar arrays could meet this demand. Concretely, the co-location of memory (DNN weight storage) and computing (analog matrix multiplications (MMs)) in crossbar arrays obviates the need to shuttle weight data, thus reducing the computing power consumption, while the use of the non-volatile memory minimizes the power consumption during idle states. Resistive, phase-change, and magneto-resistive random-access memory (RRAM, PRAM, and MRAM) and flash memory are well-known non-volatile memory types, with their own merits and drawbacks. Of these, MRAM boasts high endurance and low switching energy (with the drawback being 1b storage per cell) [1] and has been commercially embedded in CMOS logic technology, and thus MRAM is a good non-volatile memory candidate for IMC. However, previous MRAM IMC works [2]–[5] have been focused on individual crossbar arrays, which correspond only to a small fraction of a DNN.