3.4: A CMOS Operational Amplifier Achieving $\pm 5.8 \mu \mathrm{V}\ 3 \sigma$ Offset and $\pm 88\text{nV}/{{}^{\circ}}\mathrm{C}\ 3\sigma$ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique

Precision operational amplifiers (opamps) are used in a wide range of signal conditioning applications for their low offset and offset drift. Opamps using MOS-input stages are attractive for interfacing high-impedance sources thanks to their low input current. However, the offset and offset drift of MOS-input opamps are relatively high. Dynamic offset cancellation techniques such as chopping and autozeroing can be used to reduce offset and offset drift, but often at the cost of added complexity and power consumption [1]–[5]. In addition, the switching artifacts increase the input current and produce spurious tones at the switching frequencies and their harmonics [1]–[5]. A conventional 2-temperature offset trim can be applied to a MOS-input opamp but at the cost of additional heating equipment, relatively long test time, and logistics. Either done on the wafer level for high throughput or post-package level to correct packaging-induced offset, such trimming cannot be done easily in the field to correct any long-term offset drift induced by, e.g., aging. To simplify trimming, a room-temperature trimming technique is proposed in [6]; however, its offset and offset drift are still relatively high: $\pm 45\mu \mathrm{V}(3\sigma)$ and $\pm 330\text{nV}/^{\circ}\mathrm{C}(3\sigma)$ from $-40{{}^{\circ}\mathrm{C}}$ to $125{{}^{\circ}\mathrm{C}}$ respectively.