High Speed Low Power Dynamic CMOS Comparator for SAR ADCs

This work presents the design of a dynamic CMOS comparator for SAR ADCs. The proposed comparator implements three improvements, namely: (1) it introduced a shared charge technique on the output terminals to reduce the delay; (2) it employed control and switch transistors on the pre-amplifier stage to reduce power consumption and (3) it replaced the PMOS tail current with NMOS to eliminate the need of an inverted clock to reduce noise. A conventional double-tail dynamic comparator is simulated alongside the proposed comparator to assess the performance of the novelty of the proposed comparator. The use of the same aspect ratio and common test bench assured the unbiased results. Results show that with 1.2GHz clock frequency and 1.2V supply voltage, the proposed comparator consumed a total average power of 886.4uW with a delay of 18.3ps, a total noise output of 0.7mVrms and an input referred noise of 7.027uVrms. While that of the conventional comparator consumed a total average power of 997.1uW with a delay of 51.93ps, a total noise output of 27.8mVrms and an input referred noise of 278uVrms.