Dual Mode Output Capacitorless Low Dropout with Low Quiescent Current for Hearing Aid Applications

This paper presents a novel low dropout regulator (LDO) for hearing aid applications, implemented in 65 nm CMOS technology. The LDO, designed without an output capacitor, achieves a low quiescent current of 3.09 $\mu\mathbf{A}$ through subthreshold operation. It features an adaptively biased regulation mechanism with two power transistors, supporting load current range up to $500\ \mu\mathbf{A}$. The Dynamic Voltage Scaling (DVS) block offers normal and low power modes, regulating output voltages to 0.7 V and 0.9 V. Simulation results show a power consumption of $3.4 \mu\mathbf{W}$, PSRR of -75 dB at 1 kHz, line and load regulation of 1.10.7 mV/V and 0.484 mV/mA, respectively, and a settling time of 1.37 to $3.6\ \mu\mathbf{s}$. The LDO maintains 0.9 V output for input voltages between 1.1 V and 1.4 V in normal mode, and 0.7 V at 1 V input in low power mode, with a dropout voltage of 100 mV and 89.89% efficiency.