PPA-Aware Power Grid Optimization Techniques for Congested High Frequency Datapath Designs

In this paper, we present the study done on designing a robust and optimized power grid network that meets the design-specific requirements of a high-frequency networking switch. The design utilized a semi-custom approach to achieve inherent complex features like dense packing of cells and congested utilization of signal routes without impacting area/power constraints. To efficiently meet the power, performance, and area (PPA) targets, we consider specific critical structures within the design as Datapath and use a clustering grouping and placement approach to improve the layout implementation further. The methods utilized empower designers to perform efficient tradeoff analysis for higher signal resource utilization and layout quality, meeting Voltage drop (IR) and Reliability Verification (RV) constraints. The IR drop results, generated with industry-standard EMIR (Electromigration and IR) analysis tools, provide a comprehensive understanding of the improvements made with such optimization techniques, demonstrating over 17% improvement in voltage drop for the power grid enhanced custom design while maintaining operable frequency.