CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-Kyber

This paper presents highly reliable algorithm and high-speed hardware architecture for a unified modulo reduction for CRYSTALS-Kyber. This new architecture for modulo reduction is capable of operating at a maximum clock frequency of 351.62 MHz on Artix-7 FPGA platform, consuming a latency of 5 clock cycles, which is approximately 35.24% faster than state-of-the-art implementations. In this work, we have alleviated the size expansion problem of intermediate value of the conventional Barrett algorithm (which is one of the fastest and most reliable algorithm for modulo reduction, reported in literature) by suggesting a new technique, referred as “Conditional $R$-index Switching for $b$-value Minimization (CRIS-b)”. We propose a unified modulo reduction design handling both positive and negative spectrum numbers for all arithmetic modulo operations in a butterfly unit of Number Theoretic Transform(NTT).