Accelerated Design Verification Coverage Closure Using Machine Learning

With advances in technology, the complexity of functionality implemented in integrated circuits are on the rise. One of the most challenging aspects associated with complex functionality is the verification of it. Design verification should cross-check the functionality in different operating modes, input values, and module state. The verification problem gets exacerbated when we consider other challenges like (i) scalability to address the different module requirements for different market segments (ii) reducing time to market (iii) verification of corner case requirements. Given the complexity of the designs, it is not practical to do the complete verification. Hence, designs traditionally resorted to constrained random verification whereby random input stimulus is driven to the design, and the design output is verified using an independently coded model. The goodness of the verification is measured using code coverage and functional coverage. Many times during the random verification, the stimulus generated will not be adding to any incremental coverage thus resulting in more time to complete the verification. In this paper, we attempt to bridge this gap by using machine learning. The ML model is leveraged here to predict if the given randomly generated stimulus will provide incremental coverage and then the stimulus is simulated based on the prediction.