Layer-Specific Hardware Pooling Designs for CNN Accelerators

This paper proposes and explores the impact of using Combinatorial Pooling techniques - the combination of widely used Max pooling and SOTA Deviation based pooling techniques such as Absolute Average Deviation (AAD) or Binary Weighted Absolute Deviation (BWAD) or Absolute Maximum Deviation (AMD), across different layers in CNN architectures. The design-space exploration suggests the best possible combination of pooling schemes to be adopted for realizing hardware-efficient CNN accelerators in the future. The proposed Combinatorial pooling schemes offer enhanced model accuracy in AlexNet, UNet, and VGG-16 CNN architectures, besides offering substantial hardware gains, when compared to sole usage of deviation based pooling techniques. The results obtained from FPGA synthesis on Xilinx Zedboard are presented for a single cumulative unit of convolution and pooling operation for Max, AAD, BWAD and AMD methods. ASIC Synthesis results using Cadence 45 nm technology library are showcased for exhaustive combinations when implemented for all convolution and pooling layers in VGG-16 and AlexNet CNN architectures. For AlexNet, the unique sequence “110” with BWAD (BWAD-BWAD-Max), offers footprint savings of 4.27%, 14.77%, 11.87%, and 14.64%, over the regular individual pooling methods of Max, AAD, BWAD and AMD respectively. It also exhibits 6.67% increase in accuracy over the SOTA best.