Single-Event Responses of Dual- and Triple-Well Designs at the 5-nm Bulk FinFET Node

Triple-well designs are used to isolate substrate current and the resultant noise, across well regions, yielding excellent noise isolation in mixed-signal circuits. However, the presence of a deep-n-well significantly affects charge collection after a single-event (SE) strike. In this work, identical dual- and triple-well designs are evaluated using a wide range of particle linear-energy transfer (LET) values to elucidate underlying mechanisms affecting charge collection at advanced fin field-effect transistor (FinFET) technologies. Results show that SE cross sections for dual-well technology are significantly higher than that for triple-well technology at the 5-nm bulk FinFET node. Technology computer-aided design (TCAD) simulations are carried out to compare charge collection due to the drift process, diffusion process, and parasitic bipolar junction transistors (BJTs). Results show that the absence of a parasitic n-p-n BJT and the differences in the track length affecting the diffusion process are responsible for the differences in SE cross sections.