An FPGA-based NIC Architecture Design and implementation for Time-Sensitive Network

As an emerging network technology for industrial intelligent manufacturing, time-sensitive network (TSN) allows for the interconnection between fieldbuses and various industrial information systems, thus serving as a crucial conduit for the convergence of operational technology (OT) and information technology (IT) in control networks. TSN ensures the attainment of end-to-end bounded latency for time-sensitive flows through the introduction of the time-aware shaper (TAS). Existing commercial TSN solutions, such as Intel’s I210 and I225, are limited by their reliance on single-chip ASIC designs, which restrict scheduling granularity, overall efficiency, and customization capabilities. These constraints hinder the broader application and scalability of TSN in systems with numerous time-sensitive flows. To address these challenges, this paper proposes an FPGA-based TSN Network Interface Card (NIC) design that enhances scheduling precision, synchronization, and customization. FPGA-based NICs offer high flexibility and efficient parallel processing, enabling low-latency, deterministic transmission in complex, high-volume environments for industrial automation and other critical applications.