High Performance Instruction-Data Level Parallelism Based Instruction Set Architecture in RISC-V

Computer Architecture primarily revolves around functionality, organization, and efficient implementation of the desired architecture. Efficient implementation is the key principle of computer design as it enhances the performance of the processor. One of the best methods to enhance the performance of the processor is to take advantage of parallelism. In this paper, we have proposed an implementation that exploits both instruction-level parallelism and data-level parallelism to provide faster computational results with an increased throughput. Instruction-level parallelism (ILP) is motivated by the idea of overlapped execution of instructions thereby increasing the throughput of the processor. On the other hand, Data-level parallelism (DLP) is driven by the idea of operating on large chunks of data under a single instruction multiple data (SIMD) thereby enhancing the performance of the processor. The proposed implementation is designed using reduced instruction set computing (RISC)-V instruction set architecture (ISA) in GEM5 open-source tool. By the use of above mentioned proposed implementation, two 32-bit additions and two 16 × 16 multiplications using two instructions achieve 71.2% of reduction in the latency as compared with the conventional implementation.