Hierarchical Design of Higher-Order Efficient Wallace Tree Approximate Multipliers with Innovative Compressors

Multipliers are essential design elements in Digital Signal Processing (DSP) but their traditional design consumes a lot of power, area, and time. Approximate computing provides an alternative, particularly in multimedia applications where exact precision is not always necessary. Researchers have explored approximate multipliers to reduce resource usage while maintaining reasonable accuracy. However, there's a need to further optimize resource efficiency without compromising accuracy. It is also crucial to explore how to integrate approximate computing techniques with new architectures. This paper introduces a novel technique for designing approximate multipliers using 5:2 and 4:2 compressors. The approach uses exact compressors for the higher-order bits and approximate compressors for the lower order bits to break down partial products. This hybrid approach aims to improve computational efficiency and reduce resource usage in DSP applications. The study also investigates recursive design methods that combine lower-order multipliers to design higher-order multipliers for enhancing energy efficiency and area utilization. A 4x4 multiplier is designed using innovative compressors, and an 8x8 multiplier is constructed using the proposed 4x4 multipliers in a hierarchical manner. The research conducts thorough simulations to test and analyze the proposed approach. The proposed designs show notable improvements compared to the closest existing systems, with a 16.77% reduction in MRED, an 8.56% reduction in NMED, a 12.82% reduction in delay, an 8.46% reduction in area, and a 21.42 % decrease in power consumption.