An Energy Efficient Conditional Boosting Flipflop For High Performance Sense Amplification Applications

Power consumption is a major issue in modern VLSI design, along with area and performance. The flip-flop is essential to digital systems. The IP-DCO, MHLFF, CPSFF, and CPFF flip-flop topologies are compared in sub-threshold operation. This topology includes pulse-triggered and conditional methods. Recent advances in sub threshold technologies enable low-power applications. This technique decreases flip-flop power consumption. At the same frequency, a subthreshold circuit consumes less power than a strong inversion circuit. The 18nm Tanner cmos technology is utilised for design. At 1V power supply voltage, flip-flops are evaluated from every angle and measured for average power, power delay product, and power delay.