Bit-Serial RISC-V CPU Core

The 32-bit serial RISC-V CPU is a novel bit-serial CPU core that implements the RISC-V instruction set architecture. Its unique bit-serial Datapath, with an internal data width of only one bit, enables ultra-small and low-power design especially suitable for resource-limited embedded systems and FPGAs. There has been growing interest in using bit-serial over bit-parallel execution in machine learning workloads. This paper explores an 32-bit serial RISC-V CPU architecture in detail: it analyzes its diverse core modules, like the bit-serial ALU, register file interface, control logic, and memory interface. A primary focus is on analyzing the lifecycle of executing instructions on the 32-bit serial RISC-V CPU to demonstrate the difference between executing an instruction on a word-parallel CPU with thousands of wires compared to only 32 wires in a bit-serial RISC-V CPU. Most acute challenges with this approach are complexity and performance trade-offs since one must broadcast and then concatenate wires once to form a full-size processor word. For instance, while single-cycle one-stage instructions, like other ALU operations, require only one 32-cycle phase for their execution, two-icon. In light of recent trends, including the IoT, the growth and impact of sensor nodes and the increasing energy-efficiency focus of tomorrow’s accelerators, we can envision crucial application domains for bit-serial machines such as the 32-bit serial RISC-V CPU that prioritizes silicon area and energy efficiency over performance.