Implementation of In-memory Wallace-Tree Multiplier using Hybrid Majority-gates

In-memory computing with contemporary technologies like resistive-RAM (Re-RAM) provides a possible solution to the ‘von-Neumann bottleneck,’ driving current research efforts to circumvent the memory wall. Recently, various approaches have been devised to implement logics like Boolean within memory, traditional arithmetic circuits such as multipliers and adders and often require significant hardware resources when implemented Boolean operations as series. This work addresses the challenge by adopting the Wallace-Tree multiplier architecture and addition process in every phase of the Wallace-Tree has been optimized. The usage of logic of majority for addition has advantages over NAND, NOR, and IMPLY primitives. Additionally, executing numerous majority-gates (MG) within the array columns results in substantial gate-level parallelism. The approach of using hybrid MG results in a lower area footprint, outperforming all previously reported in-memory multipliers regarding efficiency of area. Moreover, the multiplier proposed with minimal modifications to its peripheral circuitry can be implemented in a standard transistor accessed memory array, making it both area and energy efficient.