Optimizing DNN Inference on Multi-accelerator SoCs at Training-Time

The demand for executing deep neural networks (DNNs) with low latency and minimal power consumption at the edge has led to the development of advanced heterogeneous systems-on-chips (SoCs) that incorporate multiple specialized computing units (CUs), such as accelerators. Offloading DNN computations to a specific CU from the available set often exposes accuracy vs efficiency tradeoffs, due to differences in their supported operations (e.g., standard versus depthwise convolution) or data representations (e.g., more/less aggressively quantized). A challenging yet unresolved issue is how to map a DNN onto these multi-CU systems to maximally exploit the parallelization possibilities while taking accuracy into account. To address this problem, we present ODiMO, a hardware-aware tool that efficiently explores fine-grain mapping of DNNs among various on-chip CUs, during the training phase. ODiMO strategically splits individual layers of the neural network and executes them in parallel on the multiple available CUs, aiming to balance the total inference energy consumption or latency with the resulting accuracy, impacted by the unique features of the different hardware units. We test our approach on CIFAR-10, CIFAR-100, and ImageNet, targeting two open-source heterogeneous SoCs, i.e., DIANA and Darkside. We obtain a rich collection of Pareto-optimal networks in the accuracy versus energy or latency space. We show that ODiMO reduces the latency of a DNN executed on the Darkside SoC by up to $8\times $ at iso-accuracy, compared to manual heuristic mappings. When targeting energy, on the same SoC, ODiMO produced up to $50.8\times $ more efficient mappings, with minimal accuracy drop $(\lt 0.3\%)$ .