Evaluation of an LC-VCO-Based ADC Architecture With a Tapped-Delay-Line Phase Quantizer

Analog-to-digital converters (ADCs) using a voltage-controlled oscillator (VCO) offer a promising approach to time-domain ADCs. Traditionally, ring-oscillator-based VCOs (RO-VCOs) have been favored for their compact size and explicit phase detection. In contrast, LC resonator-based VCOs (LC-VCOs) provide better phase noise performance, leading to improved timing. However, the LC-VCO approach encounters challenges such as implicit phase detection and linearity suppression. We propose a time-domain architecture for an LC-VCO-based ADC that employs a tapped-delay line (TDL) as a phase quantizer (PQ). This architecture includes a feedback loop designed to stabilize phase quantization through the TDL and to suppress the nonlinearities of the VCO in voltage-to-frequency conversion. The architecture corresponds to a sigma-delta ADC in the voltage domain. We present the analysis and design of the ADC architecture. The architectural concept was proven in a system using discrete components, where a signal-to-noise-and-distortion ratio (SNDR) of 71.3 dB and an effective number of bits (ENOB) of 11.5 bits were achieved for a bandwidth (BW) of 400 kHz, despite existing nonlinearities. These results confirm the feasibility of the LC-VCO-based ADC architecture although better performance can be anticipated with custom integrated circuit (IC) implementations.