Design of a Contingent Decision Equalizer Using Analog-in-Time Processing for PAMN Wireline Receivers

The need to rapidly increase per-lane data rates to meet system bandwidth demands has led to the adoption of digital equalization schemes in wireline transceivers. However, for short reach applications, mixed-mode designs offer better power and area efficiency, especially if their complexity explosion with data rates can be alleviated. This paper presents a new hybrid linear/nonlinear equalizer that unfolds the popular recurrent equalization architecture to remove any fundamental timing constraints in the wireline receiver. The modular multi-stage architecture drastically reduces the receiver complexity and enable real-time architecture tuning to improve energy efficiency. This paves the way for continual data rate enhancement with improved circuit performance. To ensure reliable performance in advanced CMOS processes, time-domain analog signal processing is used. This choice also enables linear energy scaling with data rate and allows proportional power scaling with degree of equalization. A 3-tap realization of the receiver fabricated in 28 nm CMOS process achieved a data rate of 52 Gb/s with an efficiency of 1.0 pJ/b and BER below 1e-4 with moderate ISI where channel loss at Nyquist is less than 12 dB.