Evaluation of LSI Immunity to Noise Using an Equivalent Internal Impedance Model

Power bus noise on a printed circuit board (PCB) is regarded as one of the main factors causing faulty operation of complementary metal oxide semiconductor (CMOS) large-scale integrated circuits (LSIs). It is believed that power bus noise generates a potential difference across the internal impedances of an LSI, interfering with its correct operation. In this report, we propose an immunity evaluation model based on internal impedance, and apply it to an LSI developed for this evaluation. The immunity characteristics of the LSI are also measured using the direct power injection method. Our results show a very close match between the internal voltage generated in the LSI as simulated using the model, and the experimentally measured actual immunity characteristics of the LSI.