Analysis and Design of a 16-bit Continuous-Time Incremental Delta-Sigma ADC

This paper demonstrates the design of a high-resolution continuous-time (CT) incremental delta-sigma (I-ΔΣ) analog-to-digital converter (ADC). A zero-order successive approximation register (SAR)-assisted extended counting is adopted to achieve higher resolution without affecting the thermal noise performance and conversion time. Acting like a 2-0 multi-stage noise-shaping (MASH) structure, achieving enhanced resolution and improved linearity with little power consumption is possible. Additionally, several energy-efficient techniques are adopted. Fabricated in 55-nm CMOS, the prototype occupies 0.36mm² active area and consumes 188.6μW from a 1.2-V supply. The implemented CT-IADC achieves a measured dynamic range (DR) of 96.5 dB and a signal-to-noise-and-distortion ratio (SNDR) of 95.4 dB for a maximum input of 1.9Vpp and a bandwidth of 20kHz. The measured SNDR-based Schreier figure of merit (FoM_S) is 175.4 dB, the best among the reported results for CT-IADCs. It achieves a 5-dB FoM_S improvement on the state-of-the-art works.