NOVLI-ISA: A Novel Optimized Variable-Length Inclusive Instruction Set Architecture for RV32I/E Architecture

This paper proposes a Novel, Optimized Variable-Length Inclusive ISA for RV32I/E architectures, namely, NOVLI-ISA. The main objective of this work is to reduce the code size and, if possible, the power consumption. The proposed ISA introduces new general and tailored functions within its flexible structure. The proposed ISA is demonstrated using a sample RV32I CPU with the necessary hardware modifications. Furthermore, to evaluate its feasibility, a dedicated batch optimizer was implemented for machine code compression and quantitative analysis of typical storage reduction for different programs.