An Approach for Increasing Memory Repair Efficiency

A Built-in-Redundancy-Analysis (BIRA) technique for 3D memory is proposed to improve the utilization of redundancy and to reduce the hardware overhead. It includes an algorithm for utilization of global redundancy as well as a specific new BIRA algorithm which deals with local redundancy on dies. The necessity of a new algorithm implies from a critical challenge of yield improvement for 3D memory and, specifically, for fulfilling the continuously increasing demand of per unit area storage capacity. It is proposed to improve the utilization of redundancy and to reduce the hardware overhead via a common simultaneous use of both global redundancy (shared rows, shared memory blocks, memory segments, memory instances) and local redundancy. A new BIRA algorithm for local redundancy elements differs from currently existing BIRA algorithms in a sense that instead of performing an exhaustive search of a proper set of redundancies the solution is provided automatically via a special decision table. The current decision table is based on a set of 8 repair patterns for 2 redundant rows and 2 redundant columns covering the topology of fault distribution for all possible repairable fault sets for a given memory instance. At the same time, it can be easily extended for any number of redundancy elements while existing algorithms are bringing to an essential increase while that number grows. The set is built using the methods of machine learning for determining decision preferences and it is proven that the suggested set of repair patterns is complete. A system of Boolean equations is built for each repair pattern which can be considered as a basis for transformation of the decision table to a repair circuit.