1T1R and 2T0C1R IGZO-MoS2 All-BEOL 3D Memory Cells

For system-technology co-design (STCO) of BEOL compatible beyond-Silicon heterogeneously integrated (Oxide & 2D material) materials, we investigated the monolithic 3D integration of vertically stacked 1T1R and 2T0C1R DRAM-RRAM hybrid memory array with IGZO FETs and $\text{MoS}_{2}$ analog RRAMs for low voltage switching. Our wafer-scale process $(< 400^{\circ}\mathrm{C})$ demonstrates good device performance. The ITO-enhanced IGZO selecting transistors $\left(\mathrm{I}_{\text{on}}=196.5 \mu \mathrm{A} / \mu \mathrm{m}, \mathrm{I}_{\text {off }}=1 \text{pA} / \mu \mathrm{m}\right. at \left.\mathrm{V}_{\mathrm{d}}=1 \mathrm{V}\right)$ integrated with solution deposited $\text{MoS}_{2}$ switching layer (3.6 nm), enable 1T1R memory cells with programming current $< 100\mu \mathrm{A}$ and voltage $< 1\mathrm{V}$, compatible with CMOS logic core voltages. Furthermore, to address RRAMs endurance limitations, we propose an ultra-compact vertically stacked 2T0C1R gain cell DRAM-RRAM hybrid using dual-gated IGZO FET. We also propose an all-IGZO buffer capable of 3D BEOL data pipelining for concurrent multi-stacked array operations. Such 3D analog compute-in-memory architecture significantly reduces ADC energy overheads, achieving 121 TOPS/W efficiency and 4.73 TOPS throughput.