Precise Alignment in Ultra-Thin (< 1 µm) Interlayer Wafer-Level Active Device Transfer with SOI Temporary Bonding

This study introduces a groundbreaking SOI-based temporary bonding technique for 3DIC, resolving significant challenges in thermal management and interlayer alignment. This platform can achieve interlayer thickness below 1 µm, allowing precise visible-light alignment. Integrating advanced bonding, grinding, CMP, and wet etching, it is found that high Young's modulus adhesives can enhance the stability of remaining silicon under 10 µm during grinding and later completely be removed. Additionally, our thermal-aware partitioning and placement strategies reduce peak temperatures by 7.5%. This platform paves the way for the next generation of ultra-efficient and high-performance 3DIC.