A Novel Dual-Bit Charge Trapping Flash Cell with Operation Optimization for Standalone and Embedded Universal Applications

A novel dual-bit CTF cell with a self-aligned middle select-gate is proposed. Combined with the dedicatedly-designed array architecture, the smallest $0.03\mu \mathrm{m}^{2}$ bit size is demonstrated with 55nm process. Operation optimization with DCHE programming is conducted to mitigate the TCME. Furthermore, CHH effect is observed experimentally for the first time, achieving faster erasure speed, larger MW, and wider injected hole distribution compared with BBHH erasure, resulting in better reliability combined with DCHE scheme. Process verification and measured results show that the smallest bit size is achieved with good cell performance and lower process cost, making it promising for standalone and embedded memories simultaneously.