Novel Logic & SRAM Interconnect Design for Advanced Complementary FET (CFET) Based Technology Nodes

Using our MSCO™ platform, we investigate several CFET interconnect design options to mitigate parasitics associated with the supervias to improve circuit performance. A hybrid frontside-backside (FS-BS) PDN scheme, backside signaling, and common gate architectures are proposed to eliminate the NMOS VSS super-via, PMOS drain, and PMOS gate super-vias, resulting in 6%, 4% and 11% circuit performance benefit, respectively. A novel high density CFET SRAM cell is proposed with NMOS access transistor, unused PMOS device removal from the backside and hybrid FS-BS-PDN scheme showing 60% read-delay and 24% write-delay improvement (array-level) in comparison to the PMOS access transistor counterpart with wordline super-via and tall bitline contact.