A Multi-WL Approach to Suppress Gate-Induced Drain Leakage, Floating Body Effect, and Row Hammer Effect in Array Transistor of 4F2 DRAM and 3D Stackable DRAM

Targeting the next-generation 4F2 DRAM and 3D stackable DRAM, we propose a multi-wordline (preferably 2-wordline) array transistor for 1T1C DRAM to efficiently minimize gate-induced drain leakage (GIDL), floating-body effect (FBE), and row hammer effect (RHE) simultaneously. This device concept is applicable to both 4F2 DRAM and 3D stackable DRAM, where sophisticated junction and gate work function processing engineering pose significant challenges. In addition to the main gate (MG), we insert an auxiliary gate (AG > 0V during standby) near the storage node (SN) to achieve a two-order magnitude reduction in GIDL and demonstrate negligible FBE. This work provides both experimentally measured data and 3D TCAD simulations to substantiate the significant suppression of GIDL, FBE, and RHE, which are crucial for enabling DRAM scaling in smaller cell capacitance regimes.