Improvement of Erase Performance Using p-Type Gate in IGZO Channel-Based 3D NAND Flash

A novel structure using p-doped polysilicon with a new program/erase scheme is proposed for the first time in this paper to enhance erase performance in amorphous indium gallium zinc oxide (IGZO) channel 3D-NAND Flash. In the proposed structure, the tunneling of both electrons and holes occurs simultaneously during program and erase operation. Electron tunneling is dominant at the center of the cell, while hole tunneling is dominant at the cell corners in the erase operation. By adjusting the pass voltage of adjacent cells, the programming and erasing of the cell were switched. To evaluate the program and erase performance of the proposed structure, the incremental step pulse program (ISPP) and the incremental step pulse erase (ISPE) characteristics were compared with basic IGZO channel structures and polysilicon channel structures. The proposed structure overcomes the poor erase performance of the conventional IGZO channel structure. Also, it showed better erase performance compared to the IGZO channel structure and conventional polysilicon channel structure. The program and erase performances were optimized through engineering the O/N/O layer.