Modeling of a High Precision Continuous Time Sigma Delta Modulator

Sigma-Delta ADC architecture is usually adopted in high precision ADCs. This paper presents a sigma delta modulator (SDM) model based on a single loop feedforward and feedback topology (CIFF-B), a single bit quantization, and a FIR feedback DAC. The different structures of Sigma-Delta modulator are studied using Simulink and non-ideal factors are concerned. Considering the impact of clock jitter on continuous time Sigma Delta modulators, FIR filter is added to the feedback DAC. In this paper, the system structure of the modulator adopts the pulse invariant transformation method, and the system design parameters are obtained by modeling the non-ideal factors such as clock jitter, the irrational factor of the amplifier and the clock delay. The simulation results of the proposed SDM model achieve 22.68bit of significant bits (ENOB) with 5.12MHz sample frequency.