Design and Analysis of Compact BCD Adder for Future High-Speed and Low-Power Electronic Applications

In this study, a unique design of BCD adder optimized for area and speed is proposed. The design is assessed in comparison to current techniques, with an emphasis on important key metrics such as silicon area, power utilization, and propagation latency. The 16nm, 22nm, and 32nm technologies are used to model the circuits like BCD-MFA, BCD-SCLAA and BCD-DCLAA, and the results are correlated among the circuits respectively. When the operating temperature is varied from 27°C to 107°C, the Td (delay) changes by 32.48%, 31.25% and 31.11% for the BCD-DCLAA implemented of 16 nm, 22 nm and 32 nm, respectively. The 4-bit BCD-MFA, BCD-SCLAA and BCD-DCLAA implemented with 16 nm CMOS exhibited a PDP of 5.56/6.64 fJ, 8.1417/10.386 fJ and 6.37/7.771 fJ, respectively at 27⁰C/107⁰C . Therefore, based on the examination of 3 different BCD adders considering latency, power and the product of Td and Pc, it is observed that dynamic-CLAA BCDA is more efficient and accurate. Digital watches, digital meters, digital calculators, financial systems, microcontrollers, embedded systems, and data conversion systems that require accurate decimal arithmetic all use BCD adders.